The present invention relates to a semiconductor device and an operating method of the same, and particularly relates to a technique that is effective when being applied to a semiconductor device including a MONOS memory.
A single-gate MONOS (Metal Oxide Nitride Oxide Semiconductor) memory is known as one of known non-volatile memory elements. The single-gate MONOS memory includes source and drain regions formed in a surface of a semiconductor substrate, a memory gate electrode, and a charge storage film formed between the semiconductor substrate and the memory gate electrode. In a non-volatile memory device, such MONOS memories are arranged in an array to configure a memory array in which selection of a MONOS memory in a read operation and the like can be performed by using a selecting transistor coupled in series to each MONOS memory, for example.
Japanese Unexamined Patent Application Publication No. 2004-349680 describes forming a low breakdown voltage MIS (Metal Insulator Semiconductor) transistor, a high breakdown voltage MIS transistor, a MONOS transistor, and a MIS transistor for memory selection. In this description, gate insulating films of the high breakdown voltage MIS transistor and the MIS transistor for memory selection are formed by the same insulating film.